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作者：北京廣利核系統(tǒng)工程有限公司 董玲玲，許先音，李夢(mèng)林

摘要：基于FPGA開發(fā)的核電數(shù)字化儀控系統(tǒng)（DCS）應(yīng)用環(huán)境苛刻，功能性的故障可能引起誤操作，進(jìn)而引發(fā)災(zāi)難性的后果，因此對(duì)FPGA開發(fā)的軟件功能的測(cè)試尤為重要。傳統(tǒng)的界面仿真測(cè)試驗(yàn)證效率低、可重用性差，而采用驗(yàn)證方法學(xué)的驗(yàn)證平臺(tái)的搭建又較為繁瑣，用時(shí)較多，不能滿足項(xiàng)目時(shí)間的要求。本文提出一種基于System Verilog 搭建的可重用的驗(yàn)證平臺(tái)，采用虛擬端口方法模擬外部芯片接口的功能，最后采用批處理的方式開啟驗(yàn)證平臺(tái)，實(shí)現(xiàn)自動(dòng)化的仿真測(cè)試，其接口模型、算法庫及驗(yàn)證平臺(tái)自啟動(dòng)的框架可在不同的項(xiàng)目測(cè)試
中使用，實(shí)現(xiàn)可重用性。該平臺(tái)已在公司的核電站儀控系統(tǒng)產(chǎn)品的驗(yàn)證中得到成功應(yīng)用，縮短了測(cè)試時(shí)間，并滿足安全級(jí)產(chǎn)品認(rèn)證的要求。

關(guān)鍵詞：驗(yàn)證平臺(tái)；System Verilog；重用性；仿真驗(yàn)證

Abstract: The application environment of the nuclear power digital instrument control system (DCS) developed by FPGA is harsh. Functional failure may cause misoperation,which may lead to disastrous consequences. Therefore it is particularly important to perform functional tests of the software developed by FPGA. The traditional interface simulation test verification efficiency is low and the reusability is poor, while the methodology-based verification platform is a bit complicated and takes a lot of time, which cannot meet the requirements of project time. In this paper, a reusable verification platform based on System Verilog is proposed. By using the method of virtual port to simulate the function of external chip, the verification platform is opened by batch processing to realize automatic simulation test. The verification platform can be used in different project tests to realize reusability. The platform has been successfully applied in the verification of the company's nuclear power plant control system products, which shortens the test time and meets the requirements of safety level product certification.

Key words: Testbench; System Verilog; Reusable; Simulation verification

在線預(yù)覽：一種可重用的驗(yàn)證平臺(tái)在核電FPGA仿真測(cè)試中的應(yīng)用

摘自《自動(dòng)化博覽》2019年12月刊